1. Field of the Invention
The present invention relates to a synchronization correction circuit for correcting synchronization between a packet transmission cycle and a transfer clock in a receiving device. The synchronization correction circuit according to the present invention is applied, for example, to a Bluetooth-compliant audio data processing circuit.
2. Description of Related Art
A conventional synchronization correction circuit will hereinafter be described with reference to an example where such a circuit is applied to a Bluetooth-compliant audio data processing circuit.
“Bluetooth” is one type of specification for data communications between terminals or other devices. This specification applies to various types of data communications conducted between personal computers, printers, mobile telephones, and the like, principally involving audio data.
In a Bluetooth system, communications are conducted using packets. In other words, for a sound communication packet, a packet comprising a synchronization word which is called “sync word” for short, and a payload section is used, as illustrated in FIG. 14. Here, the sync word is used by the receiver to determine the packet transmission interval. Furthermore, audio data is contained in the payload section. There are three types of packets respectively allowing an audio data volume of 10 bytes, 20 bytes and 30 bytes, to be stored in the payload section of each packet. Bluetooth specifies respective packet transmission intervals of 1.25 ms, 2.5 ms and 3.75 ms for these types of packets.
In Bluetooth, one of the communication devices, or the like, is set as a master device, the other is taken as a slave device, and bi-directional communications are conducted therebetween by means of time division multiplexing. In other words, the terminal, or the like, set as the master determines the packet transmission interval, and the terminal, or the like, set as the slave is synchronized therewith and communications are conducted therebetween. The master/slave relationship is determined by an appropriate method, for each communication. FIG. 15 is a conceptual diagram for illustrating a Bluetooth communications system. FIG. 15(A) indicates type I, namely, a case where the payload section contains 10 bytes and the packet transmission interval is 1.25 ms; FIG. 15(B) indicates type II, namely, a case where the payload section contains 20 bytes and the packet transmission interval is 2.5 ms; and FIG. 15(C) indicates type III, namely, a case where the payload section contains 30 bytes and the packet transmission interval is 3.75 ms.
FIG. 16 is a block diagram showing the composition of a conventional audio data processing circuit for use with Bluetooth. As shown in FIG. 16, this audio data processing circuit 1600 comprises a baseband processing section 1610 and 1620 are connected respectively via a bus 1630 to a CPU (Central Processing Unit) 1640. During reception, the baseband processing section 1610 extracts the payload sections from the packets and sends same to the audio data converting section 1620, whereas during transmission, it generates packets for transmitting audio data received from the audio data converting section 1620. During reception, the audio data converting section 1620 converts audio data received from the baseband processing section 1610, as necessary, and sends same to the PCM (Pulse Code Modulation) codec interface circuit in a subsequent stage, whereas during transmission, it re-converts audio data received from the PCM codec interface circuit, as necessary, and sends same to the baseband processing section 1610. Bluetooth is compatible with three types of audio data format: CVSD (Continuous Variable Slope Data modulation), A-law and μ-law. On the other hand, the PCM codec interface circuit is compatible with three types of audio data format: Linear, A-law and μ-law.
A transfer synchronization signal PCMSYNC and transfer clock PCMCLK are used for sending and receiving data between the audio data converting section 1620 and the PCM codec interface circuit. FIG. 17 illustrates a case where 8-bit/word monoaural data is sampled as 8 kHz. As is understood from the timing chart shown in FIG. 17, the transfer synchronization signal PCMSYNC specifies the transfer cycle for each word, and the transfer clock PCMCLK specifies the transfer timing for each bit forming the audio data (PCM data). One word may also be composed by 16 bits. In the case of an 8 kHz cycle for the transfer synchronization signal PCMSYNC, the cycle of the transfer clock PCMCLK will be 64 kHz or above (for 8-bit/word) or 128 kHz or above (for 16-bit/word).
Generally, the transfer clock PCMCLK is generated by the system clock of the audio data processing circuit 1600. Furthermore, the transfer synchronization signal PCMSYNC is generated by the transfer clock PCMCLK.
In communications using an audio data processing circuit 1600 of this kind (see FIG. 16), the packet transmission cycle is determined by means of the transfer synchronization signal PCMSYNC from the transmitter circuit (in other words, the circuit generating the packets). Therefore, the transmission period for the PCM data stored in this packet (see FIG. 17) is also determined by synchronization with the transfer synchronization signal PCMSYNC from the transmitter. However, the transfer synchronization signal PCMSYNC used by the receiver terminal is generated within the receiver circuit 1600. In other words, in FIG. 17, whereas the PCM data is generated so as to be synchronized with the system clock of the transmitter-side audio data processing circuit 1600, the transfer synchronization signal PCMSYNC and transfer clock PCMCLK are generated so as to be synchronized with the system clock of the receiver-side audio data processing circuit 1600.
Here, in cases where the two audio data processing circuits 1600, 1600 conducting communications are running at absolutely the same operating frequency, the PCM data and the transfer synchronization signal PCMSYNC in FIG. 17 will assume completely synchronized states. However, in actual practice, there is often a disparity between the operating frequencies of the receiver-side circuit 1600 and the transmitter-side circuit 1600. If the two circuits 1600, 1600 have different operating frequencies, then the PCM data will not be synchronized completely with the operating clock PCMCLK and the transfer synchronization signal PCMSYNC.
FIG. 18 is a timing chart giving a conceptual illustration of one example of a state where the transfer synchronization signals PCMSYNC of the master and slave do not coincide. In the example in FIG. 18, the frequency of the transfer synchronization signal PCMSYNC generated by the master device is higher than the frequency of the transfer synchronization signal PCMSYNC generated by the slave device. Therefore, on the slave side, the frequency of the received PCM data will be too high compared to the frequency of the transfer synchronization signal PCMSYNC. Consequently, an underflow will be created in the slave device when the received PCM data is transferred from the audio data converting section 1620 to the PCM codec interface circuit. In the master device, on the other hand, the frequency of the received PCM data will be too low compared to the frequency of the transfer synchronization signal PCMSYNC. Therefore, an overflow will be created in the master device when the received PCM data is transferred from the audio data converting section 1620 to the PCM codec interface circuit. If an underflow or overflow arises in the transfer of PCM data from the audio data converting section 1620 to the PCM codec interface circuit, then as a consequence, the communication quality will decline.